Tmplab - User contributions [en]

Things and borrowed things

2013-12-09T07:48:23Z

Aeris: /* Borrowed Things */

Rule of the Library :
'''Ask all the borrowers by email to return the stuff before borrowing something yourself ;-)'''
== Available Things ==

Available object (E owner)

* OmniPCX enterprise (E tmplab) http://tri.xtra-internet.com/files/File/doc%20installateur%20oxo/doc-expert-R4.pdf
* AEG Décapeuse thermique
* Dell 1600n network printer. Cartridge : P4210 or P4671 (E tmp) ftp://ftp.dell.com/Manuals/all-products/esuprt_printers_main/esuprt_printers/dell-1600n_Owner's%20Manual_fr-fr.pdf
* Canon MP600 (E ???)
* Bunch of digisparks (E Sam) http://digistump.com/category/1
* Dell SC 1435 (E Sam)
* Macbook blanc (E tmp/Sam)
* mini hp 201 (E Sam)
* HKC VGA screen (E Sam)
* Watson computer (E Sam)
* Kinect (E Sam)
* EggBot (E Sam)
* Karotz (E Sam)
* Camping Gaz soldering Iron (E Sam)

== Borrowed Things ==

* Petite caméra blanche Intel - lekernel
* <strike>devkit : AVnet Spartan 3A (celui sans nom sur la boite) - aeris</strike>
* <strike>Tournevis - Antonin/Daniel</strike>
* lecteur carte a puce - arth16 <AT> Gmaaaaaiil
* CD - Windows XP SP2 - Christian 6Bis
* <strike>Kiniou's USB Keyboard - Fred photographe du 6bis</strike>
* ACG RFID+SC reader -- Kugg
* China Mini SmartCard reader, USB cable, SIM placeholder, CD -- Kugg

== Borrowed Books ==

* <strike> [http://www.amazon.fr/Gu%C3%A9rilla-kit-techniques-nouvelles-anticapitalistes/dp/2707154059/ref=pd_bbs_sr_1?ie=UTF8&s=books&qid=1203087206&sr=8-1 "Guérilla kit" ] - Lyle</strike>
* "Hacking - the art of exploitation" - massoud : xavier.carcelle AT gmail.com
* <strike>"Du mode d'existence des objets techniques" - HK</strike>
* <strike>"AI Application Programming, by M. Tim Jones" - AlbanC</strike>
*<strike>"Python Cookbook, O'Reilly" - Alex K : alex AT petiteboitesansfond.net</strike>
* <strike>"guide to open content licenses v1.2" - Spamforfree Thiago </strike>
* Clavier Mac - Far [http://www.bestpills4weightloss.com/ best weight loss pills that work]
* <strike> Pierre Tilman, Filiou, nationalité poète, les presses du réel_ Ursula</strike>
* <strike> book-: Core... _Ursula </strike>
* Retour au meilleur des mondes - Ursula : ursula AT gastfall.org
* Unix, comment faire... - Ursula : ursula AT gastfall.org
* Art Critical Ensemble, éditions de l'éclat _Ursula : ursula AT gastfall.org
* "L'homme et ses trois éthiques" - Stéphane Lupasco + "Sociologie des réseaux sociaux" Pierre Mercklé - Karim
* Programming Ruby - The Pragmatic Programmers' Guide, de Dave Thomas avec Chad Fowler et Andy Hunt
* Agile Web Development with Rails, de Dave Thomas et David Heinemeier Hansson
* <strike> Introduction a la guerre civile, Tiqqun - Nico nicolas <__AT__> littlecleaver <DOT> com</strike>
* Storytelling - Padawan : fjacopin _AT_ lavabit.com
* Quand les banlieues brûlent - Padawan : fjacopin _AT_ lavabit.com
* <strike> Du mode d'existence des objets techniques - Padawan</strike>
* La France A Peur, une histoire sociale de l'"Insécurité" - Padawan : fjacopin _AT_ lavabit.com
* L'insurrection qui vient (Hellekin) -> Nico nicolas <__AT__> littlecleaver <DOT> com
* Design and Implementation of 4.4 BSD OS - Defree @@@@@@ Gmaaaaiiiil .com
* Fictions, Jorge Luis Borges - Jeff/6Bis : azillis _AT_ free.fr
* Le moine qui vendit sa Ferrari - Defre (pote de Arthur)
* [http://www.amazon.com/Hack-Proofing-Your-Network-Tradecraft/dp/1928994156 "Hack Proofing Your Network: Internet Tradecraft"] - arth16 <AT> Gmaaaaaiil
* <strike> Debian a 200% -- ToM</strike>
* <strike> La desobeissance civile (Henry David Thoreau) -- ToM</strike>
* <s> Du bon usage de la piraterie (Florent Latrive) -- Siltaar</s>
* <strike> Manifeste pour une desobeissance generale -- ToM</strike>
* Atlas Shrugged -- Dermiste
* Linux Device Drivers - Providence.Salumu _at_ gmail . com
* Ready, Fire, Aim -- clemATcygDOTfr
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Ikos Pegasus reverse engineering

2011-02-24T08:59:36Z

Aeris: /* How to use boundary scan with urJTAG */

= Overview =
== What? ==
A big FPGA based ASIC emulator from the late 90s. Hundreds of FPGAs, thousands of I/Os, hundreds of amperes, dozens of kilos, etc. The FPGAs are quite old (approx. 1/3 the size and 1/3 the speed of a Virtex4 XC4VLX25) but there are ''many'' of them, brute forcing designs can be usually deeply pipelined to make them fast even on slow FPGAs, and it is a great learning tool.

* The rack with the power supply can hold up to 7 boards connected via a backplane.
* One main board with:
** SCSI controller
** 8051
** CPLD
** FPGAs
** SDRAM
* 5 auxiliary boards with (each):
** 1 XC95216 CPLD
** 64 XC4036XL FPGAs
** lots of SRAM
* One auxiliary board was destructively reverse engineered, so only 4 are remaining.

Some device photos are [http://ygdes.com/ikos/ here].

See also business articles about the product and its manufacturer:
* [http://www.allbusiness.com/finance/1166622-1.html Mentor Graphics to buy Ikos Systems for 1.69 times revenue]
* [http://www.allbusiness.com/company-activities-management/product-management/6820155-1.html IKOS' VirtuaLogic Emulator Breaks DesignCompilation Time Speed Barrier]
* [http://www.thefreelibrary.com/Rendition+Selects+VirtuaLogic+Emulator+and+Retains+IKOS+Consulting...-a019815460 Rendition Selects VirtuaLogic Emulator]

There are also some reports of using the device in academia, many papers are available from the [http://www.ieeesucks.com I€€€] if you have some grease money to spare.

== Who? ==
[http://lekernel.net Lekernel] and [http://www.aerith.fr Aeris] are doing the reverse engineering, [http://www.ygdes.com Yann] provided the device and [http://www.usinette.org Alex] helped carrying it into the lab. Other contributors are welcome.

= Programming the auxiliary boards =
== Situation ==
In normal operation, the CPLD receives configuration data from the backplane (originating from the mainboard through the SCSI port) and distributes it to the FPGAs. The CPLD uses JTAG to send data to the FPGAs. The 64 FPGAs on each auxiliary board are arranged to form one big JTAG chain driven by the CPLD.

Because this mode of operation uses a proprietary protocol which is especially hard to reverse engineer since we do not have the original software and SCSI device driver, we are trying to program the boards with a JTAG probe.

== FPGA JTAG pins ==
Here is the pinout of the JTAG port on the FPGAs (in BGA packages), as published by Xilinx.
{|border="1"
|'''Signal'''
|'''Pin'''
|-
| TMS
| K30
|-
| TCK
| D31
|-
| TDI
| D30
|-
| TDO
| C4
|}

== CPLD access ==
The CPLD's JTAG port is accessible on each board with a HE10 connector following the [http://www.xilinx.com/itp/xilinx4/data/docs/pac/cables8.html MultiLINX] pinout.

{|border="1"
|Vref
|GND
|NC
|NC
|NC
|NC
|NC
|NC
|NC
|-
|NC
|TDO
|NC
|X
|TDI
|TCK
|TMS
|NC
|NC
|-
|}
Legend: X = missing pin (key), NC = No Connect

We can use [http://urjtag.org urJTAG] to access the CPLD, with the BSDL files released by Xilinx to enable boundary scan. For an unknown reason, the Xilinx iMPACT tool fails to recognize the CPLD.

=== How to use boundary scan with urJTAG ===
For Xilinx cable :
cable xpc_ext
For FTDI cable :
cable USB-to-JTAG-IF

bsdl path [path to BSDL files]
detect
instruction EXTEST
shift ir
set signal [pin name from BSDL] out 1
shift dr

== FPGA JTAG chain topology ==
All the 64 FPGAs are arranged in a daisy chain for TDI and TDO.

For TCK and TMS, the board is divided into 4 quadrants and these signals are shared within each quadrant.

[[Image:Ikos_jtag.png]]

== Connection of the FPGA JTAG chain to the CPLD ==
TCK and TMS are not directly connected to the CPLD, but go through a column of 74xx244 TTL buffers in the middle of the board. TDI and TDO are directly connected to the CPLD.

{|border="1"
|'''Signal'''
|'''Quadrant'''
|'''CPLD pin'''
|-
|TDI
|All
|96
|-
|TDO
|All
|92
|-
|TCK
|Q1
|88
|-
|TCK
|Q2
|TBD
|-
|TCK
|Q3
|TBD
|-
|TCK
|Q4
|90
|-
|TMS
|Q1
|115
|-
|TMS
|Q2
|TBD
|-
|TMS
|Q3
|TBD
|-
|TMS
|Q4
|TBD
|}

Pins can be found by soldering LEDs on the FPGA pins and then using dichotomy to isolate each signal on the CPLD. Here are the [[urJTAG commands to set all pins to 1 on the CPLD]]. This should light up all the LEDs you soldered. Set all pins to 0 using similar commands to turn off the LEDs. Then, set only half of the pins to 1, look at the LEDs and this will tell you in which half of the CPLD pins the signal you're looking for is. Repeat the technique until a single pin is found.

Fortunately, the Pegasus does not bomb when you mess up with the CPLD, at least when only one board is inserted with all its FPGAs desoldered.

== LEDs ==
Each auxiliary board has 2 LEDs in the front. They are connected to CPLD pins 58 and 86 in current sink (active low) mode. They can be useful to test your CPLD boundary scan setup.

= Design tools =
== Synthesis ==
You will need to use Synplify which supports the XC4000 family of FPGAs. There is no Xst support whatsoever.

== Place and route ==
Synplify generates an EDIF netlist which can be fed to the [http://www.xilinx.com/tools/classics.htm ISE Classics] tools for place and route and bitstream generation.

== FPGA JTAG programming ==
TODO
* JTAG tunnelling through the CPLD boundary scan?
* or reprogram the CPLD to re-route JTAG somewhere else?
* does iMPACT support XC4000s?
* it seems urJTAG has some FPGA programming support.

= Interconnect =
Once we have full JTAG access to the FPGAs, the reverse engineering of the interconnect can be vastly automated by using techniques such as that of [http://nsa.unaligned.org NSA@home].

== FPGA to FPGA ==
TBD

== FPGA to SRAM ==
TBD

== FPGA to I/O port ==
TBD

== Board to board ==
TBD

Ikos Pegasus reverse engineering

2010-10-28T11:10:23Z

Aeris: Undo revision 2850 by Aeris (Talk)

= Overview =
== What? ==
A big FPGA based ASIC emulator from the late 90s. Hundreds of FPGAs, thousands of I/Os, hundreds of amperes, dozens of kilos, etc. The FPGAs are quite old (approx. 1/3 the size and 1/3 the speed of a Virtex4 XC4VLX25) but there are ''many'' of them, brute forcing designs can be usually deeply pipelined to make them fast even on slow FPGAs, and it is a great learning tool.

* The rack with the power supply can hold up to 7 boards connected via a backplane.
* One main board with:
** SCSI controller
** 8051
** CPLD
** FPGAs
** SDRAM
* 5 auxiliary boards with (each):
** 1 XC95216 CPLD
** 64 XC4036XL FPGAs
** lots of SRAM
* One auxiliary board was destructively reverse engineered, so only 4 are remaining.

Some device photos are [http://ygdes.com/ikos/ here].

See also business articles about the product and its manufacturer:
* [http://www.allbusiness.com/finance/1166622-1.html Mentor Graphics to buy Ikos Systems for 1.69 times revenue]
* [http://www.allbusiness.com/company-activities-management/product-management/6820155-1.html IKOS' VirtuaLogic Emulator Breaks DesignCompilation Time Speed Barrier]
* [http://www.thefreelibrary.com/Rendition+Selects+VirtuaLogic+Emulator+and+Retains+IKOS+Consulting...-a019815460 Rendition Selects VirtuaLogic Emulator]

There are also some reports of using the device in academia, many papers are available from the [http://www.ieeesucks.com I€€€] if you have some grease money to spare.

== Who? ==
[http://lekernel.net Lekernel] and [http://www.aerith.fr Aeris] are doing the reverse engineering, [http://www.ygdes.com Yann] provided the device and [http://www.usinette.org Alex] helped carrying it into the lab. Other contributors are welcome.

= Programming the auxiliary boards =
== Situation ==
In normal operation, the CPLD receives configuration data from the backplane (originating from the mainboard through the SCSI port) and distributes it to the FPGAs. The CPLD uses JTAG to send data to the FPGAs. The 64 FPGAs on each auxiliary board are arranged to form one big JTAG chain driven by the CPLD.

Because this mode of operation uses a proprietary protocol which is especially hard to reverse engineer since we do not have the original software and SCSI device driver, we are trying to program the boards with a JTAG probe.

== FPGA JTAG pins ==
Here is the pinout of the JTAG port on the FPGAs (in BGA packages), as published by Xilinx.
{|border="1"
|'''Signal'''
|'''Pin'''
|-
| TMS
| K30
|-
| TCK
| D31
|-
| TDI
| D30
|-
| TDO
| C4
|}

== CPLD access ==
The CPLD's JTAG port is accessible on each board with a HE10 connector following the [http://www.xilinx.com/itp/xilinx4/data/docs/pac/cables8.html MultiLINX] pinout.

{|border="1"
|Vref
|GND
|NC
|NC
|NC
|NC
|NC
|NC
|NC
|-
|NC
|TDO
|NC
|X
|TDI
|TCK
|TMS
|NC
|NC
|-
|}
Legend: X = missing pin (key), NC = No Connect

We can use [http://urjtag.org urJTAG] to access the CPLD, with the BSDL files released by Xilinx to enable boundary scan. For an unknown reason, the Xilinx iMPACT tool fails to recognize the CPLD.

=== How to use boundary scan with urJTAG ===
cable xpc_ext
bsdl path [path to BSDL files]
detect
instruction EXTEST
shift ir
set signal [pin name from BSDL] out 1
shift dr

== FPGA JTAG chain topology ==
All the 64 FPGAs are arranged in a daisy chain for TDI and TDO.

For TCK and TMS, the board is divided into 4 quadrants and these signals are shared within each quadrant.

[[Image:Ikos_jtag.png]]

== Connection of the FPGA JTAG chain to the CPLD ==
TCK and TMS are not directly connected to the CPLD, but go through a column of 74xx244 TTL buffers in the middle of the board. TDI and TDO are directly connected to the CPLD.

{|border="1"
|'''Signal'''
|'''Quadrant'''
|'''CPLD pin'''
|-
|TDI
|All
|96
|-
|TDO
|All
|92
|-
|TCK
|Q1
|88
|-
|TCK
|Q2
|TBD
|-
|TCK
|Q3
|TBD
|-
|TCK
|Q4
|90
|-
|TMS
|Q1
|115
|-
|TMS
|Q2
|TBD
|-
|TMS
|Q3
|TBD
|-
|TMS
|Q4
|TBD
|}

Pins can be found by soldering LEDs on the FPGA pins and then using dichotomy to isolate each signal on the CPLD. Here are the [[urJTAG commands to set all pins to 1 on the CPLD]]. This should light up all the LEDs you soldered. Set all pins to 0 using similar commands to turn off the LEDs. Then, set only half of the pins to 1, look at the LEDs and this will tell you in which half of the CPLD pins the signal you're looking for is. Repeat the technique until a single pin is found.

Fortunately, the Pegasus does not bomb when you mess up with the CPLD, at least when only one board is inserted with all its FPGAs desoldered.

== LEDs ==
Each auxiliary board has 2 LEDs in the front. They are connected to CPLD pins 58 and 86 in current sink (active low) mode. They can be useful to test your CPLD boundary scan setup.

= Design tools =
== Synthesis ==
You will need to use Synplify which supports the XC4000 family of FPGAs. There is no Xst support whatsoever.

== Place and route ==
Synplify generates an EDIF netlist which can be fed to the [http://www.xilinx.com/tools/classics.htm ISE Classics] tools for place and route and bitstream generation.

== FPGA JTAG programming ==
TODO
* JTAG tunnelling through the CPLD boundary scan?
* or reprogram the CPLD to re-route JTAG somewhere else?
* does iMPACT support XC4000s?
* it seems urJTAG has some FPGA programming support.

= Interconnect =
Once we have full JTAG access to the FPGAs, the reverse engineering of the interconnect can be vastly automated by using techniques such as that of [http://nsa.unaligned.org NSA@home].

== FPGA to FPGA ==
TBD

== FPGA to SRAM ==
TBD

== FPGA to I/O port ==
TBD

== Board to board ==
TBD

Ikos Pegasus reverse engineering

2010-10-28T11:09:39Z

Aeris: /* What? */

= Overview =
== What? ==
A big FPGA based ASIC emulator from the late 90s. Hundreds of FPGAs, thousands of I/Os, hundreds of amperes, dozens of kilos, etc. The FPGAs are quite old (approx. 1/3 the size and 1/3 the speed of a Virtex4 XC4VLX25) but there are ''many'' of them, brute forcing designs can be usually deeply pipelined to make them fast even on slow FPGAs, and it is a great learning tool.

* The rack with the power supply can hold up to 6 boards connected via a backplane.
* One main board with:
** SCSI controller
** 8051
** CPLD
** FPGAs
** SDRAM
* 5 auxiliary boards with (each):
** 1 XC95216 CPLD
** 64 XC4036XL FPGAs
** lots of SRAM
* One auxiliary board was destructively reverse engineered, so only 4 are remaining.

Some device photos are [http://ygdes.com/ikos/ here].

See also business articles about the product and its manufacturer:
* [http://www.allbusiness.com/finance/1166622-1.html Mentor Graphics to buy Ikos Systems for 1.69 times revenue]
* [http://www.allbusiness.com/company-activities-management/product-management/6820155-1.html IKOS' VirtuaLogic Emulator Breaks DesignCompilation Time Speed Barrier]
* [http://www.thefreelibrary.com/Rendition+Selects+VirtuaLogic+Emulator+and+Retains+IKOS+Consulting...-a019815460 Rendition Selects VirtuaLogic Emulator]

There are also some reports of using the device in academia, many papers are available from the [http://www.ieeesucks.com I€€€] if you have some grease money to spare.

== Who? ==
[http://lekernel.net Lekernel] and [http://www.aerith.fr Aeris] are doing the reverse engineering, [http://www.ygdes.com Yann] provided the device and [http://www.usinette.org Alex] helped carrying it into the lab. Other contributors are welcome.

= Programming the auxiliary boards =
== Situation ==
In normal operation, the CPLD receives configuration data from the backplane (originating from the mainboard through the SCSI port) and distributes it to the FPGAs. The CPLD uses JTAG to send data to the FPGAs. The 64 FPGAs on each auxiliary board are arranged to form one big JTAG chain driven by the CPLD.

Because this mode of operation uses a proprietary protocol which is especially hard to reverse engineer since we do not have the original software and SCSI device driver, we are trying to program the boards with a JTAG probe.

== FPGA JTAG pins ==
Here is the pinout of the JTAG port on the FPGAs (in BGA packages), as published by Xilinx.
{|border="1"
|'''Signal'''
|'''Pin'''
|-
| TMS
| K30
|-
| TCK
| D31
|-
| TDI
| D30
|-
| TDO
| C4
|}

== CPLD access ==
The CPLD's JTAG port is accessible on each board with a HE10 connector following the [http://www.xilinx.com/itp/xilinx4/data/docs/pac/cables8.html MultiLINX] pinout.

{|border="1"
|Vref
|GND
|NC
|NC
|NC
|NC
|NC
|NC
|NC
|-
|NC
|TDO
|NC
|X
|TDI
|TCK
|TMS
|NC
|NC
|-
|}
Legend: X = missing pin (key), NC = No Connect

We can use [http://urjtag.org urJTAG] to access the CPLD, with the BSDL files released by Xilinx to enable boundary scan. For an unknown reason, the Xilinx iMPACT tool fails to recognize the CPLD.

=== How to use boundary scan with urJTAG ===
cable xpc_ext
bsdl path [path to BSDL files]
detect
instruction EXTEST
shift ir
set signal [pin name from BSDL] out 1
shift dr

== FPGA JTAG chain topology ==
All the 64 FPGAs are arranged in a daisy chain for TDI and TDO.

For TCK and TMS, the board is divided into 4 quadrants and these signals are shared within each quadrant.

[[Image:Ikos_jtag.png]]

== Connection of the FPGA JTAG chain to the CPLD ==
TCK and TMS are not directly connected to the CPLD, but go through a column of 74xx244 TTL buffers in the middle of the board. TDI and TDO are directly connected to the CPLD.

{|border="1"
|'''Signal'''
|'''Quadrant'''
|'''CPLD pin'''
|-
|TDI
|All
|96
|-
|TDO
|All
|92
|-
|TCK
|Q1
|88
|-
|TCK
|Q2
|TBD
|-
|TCK
|Q3
|TBD
|-
|TCK
|Q4
|90
|-
|TMS
|Q1
|115
|-
|TMS
|Q2
|TBD
|-
|TMS
|Q3
|TBD
|-
|TMS
|Q4
|TBD
|}

Pins can be found by soldering LEDs on the FPGA pins and then using dichotomy to isolate each signal on the CPLD. Here are the [[urJTAG commands to set all pins to 1 on the CPLD]]. This should light up all the LEDs you soldered. Set all pins to 0 using similar commands to turn off the LEDs. Then, set only half of the pins to 1, look at the LEDs and this will tell you in which half of the CPLD pins the signal you're looking for is. Repeat the technique until a single pin is found.

Fortunately, the Pegasus does not bomb when you mess up with the CPLD, at least when only one board is inserted with all its FPGAs desoldered.

== LEDs ==
Each auxiliary board has 2 LEDs in the front. They are connected to CPLD pins 58 and 86 in current sink (active low) mode. They can be useful to test your CPLD boundary scan setup.

= Design tools =
== Synthesis ==
You will need to use Synplify which supports the XC4000 family of FPGAs. There is no Xst support whatsoever.

== Place and route ==
Synplify generates an EDIF netlist which can be fed to the [http://www.xilinx.com/tools/classics.htm ISE Classics] tools for place and route and bitstream generation.

== FPGA JTAG programming ==
TODO
* JTAG tunnelling through the CPLD boundary scan?
* or reprogram the CPLD to re-route JTAG somewhere else?
* does iMPACT support XC4000s?
* it seems urJTAG has some FPGA programming support.

= Interconnect =
Once we have full JTAG access to the FPGAs, the reverse engineering of the interconnect can be vastly automated by using techniques such as that of [http://nsa.unaligned.org NSA@home].

== FPGA to FPGA ==
TBD

== FPGA to SRAM ==
TBD

== FPGA to I/O port ==
TBD

== Board to board ==
TBD

Things and borrowed things

2010-10-16T19:55:55Z

Aeris:

Rule of the Library :
'''Ask all the borrowers by email to return the stuff before borrowing something yourself ;-)'''

* devkit : AVnet Spartan 3A (celui sans nom sur la boite) - aeris : build_mail(tmplab, ansible, fr);
* <strike>Tournevis - Antonin/Daniel</strike>
* <strike>Book [http://www.amazon.fr/Gu%C3%A9rilla-kit-techniques-nouvelles-anticapitalistes/dp/2707154059/ref=pd_bbs_sr_1?ie=UTF8&s=books&qid=1203087206&sr=8-1 "Guérilla kit" ] - Lyle</strike>
* Book - "Hacking - the art of exploitation" - massoud : xavier.carcelle AT gmail.com
* <strike>Book - "Du mode d'existence des objets techniques" - HK</strike>
* <strike>Book - "AI Application Programming, by M. Tim Jones" - AlbanC</strike>
*<strike> Book - "Python Cookbook, O'Reilly" - Alex K : alex AT petiteboitesansfond.net</strike>
* CD - Windows XP SP2 - Christian 6Bis
* <strike>Book - "guide to open content licenses v1.2" - Spamforfree Thiago </strike>
* Clavier Mac - Far
* <strike>book : Pierre Tilman, Filiou, nationalité poète, les presses du réel_ Ursula</strike>
* <strike> book-: Core... _Ursula </strike>
* book : Retour au meilleur des mondes - Ursula : ursula AT gastfall.org
* book : Unix, comment faire... - Ursula : ursula AT gastfall.org
* book : Art Critical Ensemble, éditions de l'éclat _Ursula : ursula AT gastfall.org
* book : "L'homme et ses trois éthiques" - Stéphane Lupasco + "Sociologie des réseaux sociaux" Pierre Mercklé - Karim
* book : Programming Ruby - The Pragmatic Programmers' Guide, de Dave Thomas avec Chad Fowler et Andy Hunt
* book : Agile Web Development with Rails, de Dave Thomas et David Heinemeier Hansson
* <strike>Kiniou's USB Keyboard - Fred photographe du 6bis</strike>
* <strike>book : Introduction a la guerre civile, Tiqqun - Nico nicolas <__AT__> littlecleaver <DOT> com</strike>
* book : Storytelling - Padawan : fjacopin _AT_ lavabit.com
* book : Quand les banlieues brûlent - Padawan : fjacopin _AT_ lavabit.com
* <strike>book : Du mode d'existence des objets techniques - Padawan</strike>
* book : La France A Peur, une histoire sociale de l'"Insécurité" - Padawan : fjacopin _AT_ lavabit.com
* book : L'insurrection qui vient (Hellekin) -> Nico nicolas <__AT__> littlecleaver <DOT> com
* lecteur carte a puce - arth16 <AT> Gmaaaaaiil
* book : Design and Implementation of 4.4 BSD OS - Defree @@@@@@ Gmaaaaiiiil .com
* book : Fictions, Jorge Luis Borges - Jeff/6Bis : azillis _AT_ free.fr
* book : Le moine qui vendit sa Ferrari - Defre (pote de Arthur)
* book : [http://www.amazon.com/Hack-Proofing-Your-Network-Tradecraft/dp/1928994156 "Hack Proofing Your Network: Internet Tradecraft"] - arth16 <AT> Gmaaaaaiil
* book : Debian a 200% -- ToM
* book : La desobeissance civile (Henry David Thoreau) -- ToM
* book : Du bon usage de la piraterie (Florent Latrive) -- ToM
* book : Manifeste pour une desobeissance generale -- ToM
* book : Atlas Shrugged -- Dermiste
* ACG RFID+SC reader -- Kugg
* China Mini SmartCard reader, USB cable, SIM placeholder, CD -- Kugg
* Book: Linux Device Drivers - Providence.Salumu _at_ gmail . com